1. Field of the Invention
The present invention relates to a semiconductor memory device with a double-gate structure having a floating gate electrode and control gate electrode.
2. Description of the Related Art
A cell transistor of a flash memory serving as a nonvolatile semiconductor memory has a double-gate structure including a floating gate electrode and control gate electrode. In this flash memory, the breakdown voltage of the transistor of the peripheral circuit becomes low as the microfabrication of memory cells progresses. Since a drop in maximum operating voltage is unavoidable, reduction of write and erase voltages is an important challenge. To efficiently inject electrons from the Si substrate to the floating gate electrode even at a low voltage, (a) the tunnel insulating film is made thin or (b) the capacitance of the interelectrode insulating film is increased to apply a high electric field to the tunnel insulating film.
In the method (a), however, when charge holding is taken into consideration, the thinning of the tunnel insulating film is limited. Detailed examples of the method (b) are (1) increasing the contact area between the floating gate electrode and the interelectrode insulating film (e.g., JP-A 2002-50703 (KOKAI) (patent reference 1)), (2) making the interelectrode insulating film thin (e.g., JP-A 8-17945 (KOKAI) (patent reference 2)), and (3) using a high-K insulating film as the interelectrode insulating film (e.g., JP-A 2003-168749 (KOKAI) (patent reference 3)).
In the method (1), since the control gate electrode is provided around the floating gate electrode, the cell interval can hardly be reduced. That is, the above-described problem is hard to solve because the scaling rule (4F2) of the unit cell area cannot be satisfied in principle. In the method (2), it is difficult to suppress the leakage current between the floating gate electrode and the control gate electrode, and various operation errors occur. In the method (3), when a high-K insulating film (high dielectric constant insulating film) made of an oxide is formed on the floating gate electrode made of polysilicon as ever, a low-K interface layer (low dielectric constant interface layer) mainly containing SiO2 is readily formed due to oxidation of the polysilicon. The low-K interface layer is hard to remove in the process. When the low-K interface layer is formed, the capacitances of the low-K interface layer and high-K insulating film are connected in series, and the effective capacitance of the interelectrode insulating film decreases. Even when a method of forming, as a floating gate electrode, a conductive oxide such as RuO2 or IrO2 on polysilicon is employed, as in patent reference 2, another low-K interface layer is readily formed because of reaction between the oxide and polysilicon. Even when the floating gate electrode is changed from polysilicon to a metal or conductive metal nitride to prevent formation of the low-K interface layer, the metal may form a reaction layer on the interface of the tunnel insulating film or interelectrode insulating film. Alternatively, the metal may be diffused to the tunnel insulating film to cause dielectric breakdown. As described above, difficulties in the process remain in the method (3).
A metal ferroelectric metal insulator semiconductor FET (MFMISFET) structure is known, in which a ferroelectric material is used for the interelectrode insulating film. However, a ferroelectric holds excessive charges because polarization occurs. In addition, since the dielectric film itself is fatigued by repetitive polarization in injecting charges into and removing them from the floating gate electrode, the polarization amount decreases, i.e., a so-called fatigue characteristic exists. For these reasons, threshold control is difficult, resulting in a problem of reliability.
There is also a silicon insulator metal insulator silicon (SIMIS) transistor disclosed in patent reference 4 (JP-A 2003-46004 (KOKAI)). In the SIMIS transistor, the floating gate electrode is made of a conductive oxide (M). The control gate electrode is made of silicon (S). The interelectrode insulating film is made of a compound (I) of silicon (S) and oxygen separated from a conductive oxide (M). However, the SIMIS transistor has the following problems. First, when a semiconductor is used for the control gate electrode, a depletion layer is formed upon applying a voltage to it. As a result, the capacitances of the depletion layer and interelectrode insulating film are connected in series, and the effective capacitance of the interelectrode insulating film decreases. Second, since the semiconductor of the control gate electrode reacts with the insulating film, a low-K interface oxide layer of SiO2 or silicate is formed on the interface between the control gate electrode and the interelectrode insulating film. Hence, the capacitances of the interface oxide layer and interelectrode insulating film are connected in series, and the effective capacitance decreases even in this case. Third, when the interelectrode insulating film contains the semiconductor material of the control gate electrode, e.g., silicon, the interelectrode insulating film changes to silicate. Hence, the dielectric constant decreases, and the capacitance of the interelectrode insulating film consequently decreases.